1. Field of the Invention
The present invention relates generally to an amplifier for use in a wireless communication system, and in particular to a low noise amplifier for use in a radio frequency receiver.
2. Description of the Related Art
With the explosive growth in the commercial wireless telecommunications market, a greater need is seen for lower cost and more highly integrated telecommunications equipment. Integrated semiconductor devices provide the possibility of meeting both needs. For example, silicon based devices may provide the necessary characteristics to address a wide range of applications. CMOS (Complementary Metal Oxide Semiconductor) technology is becoming feasible for high frequency analog applications that were traditionally built with more expensive technologies such as bipolar devices. Sub-micrometer CMOS technologies now exhibit sufficient performance for RF (Radio Frequency) applications in a few gigahertz ranges. However, using a standard CMOS technology, the design of amplifiers for use at high frequencies requires more detailed considerations than those for use at low frequencies.
In FIG. 1 is shown a super-heterodyne architecture of the type that is widely used in modem wireless communications handsets. The receiver includes an antenna 10 having an output connected to a radio frequency (RF) filter 11. The filter output is connected to a low noise amplifier 12 that in turn is connected to an image filter 13. The image filter 13 output is fed to a mixer 14 which has a second input connected to a local oscillator (LO) signal 15. The output of the mixer 14 is provided to an intermediate frequency (IF) filter 16. The output of the IF filter is used in the communications system in a way that is well known.
This architecture is capable of providing high reliability and stable performance in mobile communications. In super-heterodyne receivers, the image frequency presents a problem because the image frequency is superimposed on the desired signal. In order to solve this problem and provide removal, or rejection, of the image frequency signal, the super-heterodyne receiver front-end can consist of any of several topologies. Especially useful approaches are the use of an image rejection filter component in a Hartley architecture or a Weaver architecture.
Modem radio frequency receivers are often provided on a semiconductor chip to provide the advantages of lower cost, greater compactness and reduced power consumption. The chip is indicated in FIG. 1 by the solid line 18 enclosing the low noise amplifier 12, local oscillator 15, mixer 14 and IF filter 16. Currently, most of the commercially available radio frequency receivers use off-chip passive bandpass filters, such as ceramic or surface acoustic wave (SAW) filters, because the off-chip filters provide the most robust solution to the image rejection problem. As has been well known for years, surface acoustic wave bandpass filters have a number of advantages, for example, no power consumption, no linearity degradation, and extraordinarily high quality factor. However, the high cost and large size of such separate bandpass filters make these filters less attractive for use in the next generation receivers. The conventional receiver system of FIG. 1 uses an external filter for image rejection. Specifically, the RF filter 11 and image filter 13 are provided as external components to the chip 18.
The current, off-chip passive filters, such as surface acoustic wave filters or ceramic filters, are used for image frequency rejection, but these bulky filters are the major impediment to raising the level of integration of the radio frequency circuit since they cannot be easily integrated. Systems using these filters have a relatively high cost and large size. Therefore, to decrease the circuit size, monolithic integration of the filter with the other electrical devices of the receiver circuit is being researched.
In applications for use at frequencies below 3 GHz, monolithic circuits are provided using an image rejection mixer for phase cancellation to satisfy an image rejection specification of better than 41 dB. Practical systems require higher values of image rejection. As such, it would be desirable to combine an on-chip image filter with an integrated image reject mixer to obtain a very high on-chip image rejection.
When a wide range of signal powers is received by an antenna in a wireless communications system, the system requires the addition of a variable gain stage. The variable gain function is generally provided in later stages in the radio receiver system. For example, in FIG. 2 is provided a variable gain amplifier 17 at the output of the IF filter 16. The variable gain amplifier includes a control lead 18, as is well known, for controlling the output gain of the variable gain stage to compensate for changes in the power of the received signal.
If the variable gain function is provided at the early stages in the system such as using a low noise amplifier (LNA) 12 a such as shown in FIG. 2, then the gain variation is being made in the presence of minimum power signals and the signal-to-noise ratio increases. If instead the gain control is provided later in the receiver system while in the presence of maximum power signals, the last stage of the receiver is not saturated. Furthermore, with such gain controllable low noise amplifiers (LNA), the target dynamic range of the VGA (Variable Gain Amplifier) 20 tends to be degraded.
A low noise amplifier (LNA) is used in the RF receiver in a wireless communication application to obtain the necessary power gain and decreasing the noise factor (NF). Conventional low noise amplifiers have high power consumption at radio frequencies to satisfy the required power gain and to provide the characteristics necessary in an RF receiver application. The conventional LNA uses a one unit common source amplifier structure as shown in FIG. 3 configured as a cascode amplifier.
In particular, the amplifier circuit of FIG. 3 includes a first FET 45 connected with a gate inductor 46 at its gate lead, through which is fed the input signal of the amplifier circuit. The source of the FET 45 is connected through a source inductor 47 to ground. The drain of the FET 45 is connected to a source of a second FET 43 at a node 44. The drain of the second FET 43 is connected through a drain inductor 41 to the supply voltage VDD. A bias voltage Vbias is connected at the gate of the second FET 43. A capacitor 42 is connected to the drain of the second FET 43 as well to provide the output signal for the amplifier through the capacitor.
Operationally, in FIG. 3 in order to achieve low noise and to provide power matching at the same time, the source inductor 47, also denoted Ls in the drawing, is used. When an inductor having a high quality factor is used for this source degeneration function, the result is that the amplifier has good noise performance. The bonding wire to the chip has been used as the inductor for source degeneration, and its length is selected by considering a minimum size at for the chip layout and for bonding. The drain inductor 41, also denoted Ld, the source inductor 47 and the gate inductor 46, also denoted Lg in the drawing, as well as the capacitor 42, also denoted C1, are external elements. The gate inductor 46 and the source inductor 47 are used for matching input impedance, and the drain inductor 41 and capacitor  42 are used for matching output impedance. The bias signal Vbias is supplied to the gate of the transistor 43, also denoted M2 on the drawing. The elements within the dashed line are on the chip. In this structure, the signal is amplified by the gain of the cascode structure of the two transistors 45 and 43.
Amplifiers of this type are used in wireless communications. Wireless communications systems have exhibited remarkable growth over the past decade. Wireless voice and data applications are being enabled by rapidly emerging wireless technologies, such as cellular telephony, personal communications systems and wireless local area network (WLANs), to name a few. Digital modulation techniques, miniaturization of transceivers due to advances in monolithic integrated circuit design and the development of high frequency, microwave and millimeter wave RF systems in both the licensed and unlicensed bands have all contributed to improving the quality and bandwidth capacity of these systems and to reducing the size and costs of the components.
The LNA (Low Noise Amplifier) is a critical front end component of a wireless receiver. As noted above, its function is to take the relatively weak signal received at the antenna and, after filtering of the signal, amplify it with maximum power transfer and with a minimum of added noise for further processing (referred to as down conversion, etc.). The maximum power transfer is achieved by designing the LNA to have an input impedance that matches a characteristic input impedance of the antenna, which is commonly 50 ohms. Thus, a true concurrent LNA, as a critical front end component of a concurrent receiver, must be capable of (1) matching the characteristic input impedance of the received signal at the antenna at the respective frequency band; (2) simultaneously amplifying the received signal(s); and (3) accomplishing the above with minimum added electrical noise.